COMPUTER ARITHMETIC
A basic operation in all digital computers is the addition or subtraction of two numbers. Arithmetic operations occur at the machine instruction level. They are implemented, along with basic logic functions such as AND,OR, NOT, and exclusive –OR (XOR), in the arithmetic logic unit(ALU) subsystem of the processor. We use logic Circuits to implement arithmetic operations, The time needed to perform and addition operation affects the processor’s performance. Multiply and divide operations, which require more complex circuitry than either addition or subtraction operations, also affect performance. We present some of the techniques used in modern computers to perform arithmetic operations at high speed.
Compared with arithmetic operations, logic operations are simple to implement using combinational circuitry. They require only independent Boolean operations on individual bit positions of the operands, whereas carry/borrow lateral signals are required in arithmetic operations.
ADDITION AND SUBTRACTION OF SIGNED NUMBERS
There will arise instances when we need to express numbers that are less than zero. These numbers are called signed numbers and consist of positive(+) and
negative(-) numbers. Positive numbers are greater than zero and negative numbers are less than zero.
Positive and negative whole numbers are called integers while signed fractions and decimals are called rational numbers. It is not necessary to write the + for a positive number unless you want to draw attention to the fact that it is positive. The negative sign must always in used for a negative number.
A number line for integers continues indefinitely in both the negative and positive directions. Numbers get smaller as we proceed to the left and larger to the right. The opposite of a number is the number the same distance from zero but in the opposite direction.
In order to perform operations with signed numbers, we need to define the absolute value of a number. The absolute value of a number, symbolized by placing the number between 2 vertical bars (l l) is defined to be the distance that number is located from zero on a number line without regard to the direction.
• |3| = 3
• |-5| = 5
When you add two numbers with the same signs add the absolute values, and write the sum (the answer) with the sign of the numbers. If the sign is positive, it is commonly omitted.
5 + 16 = 21
-12 + -15 = -27
Binary Addition Basic Rules for Binary Addition
0+0 = 0 0 plus 0 equals 0
0+1 = 1 0 plus 1 equals 1
1+0 = 1 1 plus 0 equals 1
1+1 = 10 1 plus 1 equals 0
with a carry of 1 (binary 2)
The technique of addition for binary numbers is similar to that for decimal numbers, except that a 1 is carried to the next column after two 1s are added.
Example: Add the numbers 310 and 110 in binary form.
Solution
The numbers, in binary form, are 11 and 01.
11
01
100
In the right-hand column, 1 + 1 = 0 with a carry of 1 to the next column.
In the next column, 1+0+1 = 0 with a carry of 1 to the next column.
In the left-hand column, 1 + 0 + 0 = 1. Thus, in binary, 11 + 01 = 100 = 410.
Binary Subtraction Basic Rules for Binary Subtraction
0 − 0 = 0 0 minus 0 equals 0
1 − 1 = 0 1 minus 1 equals 0
1 − 0 = 1 1 minus 0 equals 1
10 − 1 = 1 10 minus 1 equals 1
Example: Subtract 310 = 11 from 510 = 101 in binary form.
Solution
The subtraction procedure is shown below.
1 0 1
− 0 1 1
0
1 0 1
− 0 1 1
0
1 0 1
− 0 1 1
1 0
1 0 1
− 0 1 1
0 1 0
Starting from the left, the first array is the subtraction in the right hand column. In the second array, a 1 is borrowed from the third column for the middle column at the top and paid back at the bottom of the third column. The third array is the subtraction 10 − 1 = 1 in the middle column. The final array is the subtraction 1 − 1 = 0 and the final answer is thus 10 = 210.
Friday, March 25, 2011
Tuesday, March 22, 2011
Interrupts
5Q. What is interrupt ? Explain Priority interrupt and Daisy chain interrupt and parallel priority interrupt system with necessary diagram?
Ans : The program enters a wait loop in which it repeatedly tests the device status. During this period, the processor is not performing any useful computation. There are many situations where other tasks can be performed while waiting for an I/O device to become ready. To allow this to happen, we can arrange for the I/O device to alert the processor when it becomes ready. It can do so by sending a hardware signal called an interrupt to the processor.
Priority Interrupt: A priority interrupt is a system that establishes a priority over the various sources to determine the condition which is to be serviced first, when two or more requests arrive simultaneously.
The system may also determine which conditions are permitted to interrupt the computer while another interrupt is being serviced. Higher priority interrupt levels are assigned to requests which, if delay or interrupted, could have serious consequences. When two devices interrupt the computer at the same time, the computer services the device, with the higher priority first.
Establishing the priority of simultaneous interrupts can be done by software or hardware. A polling procedure is used to identify the highest priority source by software means. In this method there is one common branch addresses for all interrupts the Program that takes care of interrupts begins of the branch address and polls the interrupt sources in sequence. The order in which they are tested determines the priority of each interrupt.
The initial service routine for all interrupts consists of a program that tests the interrupt sources in sequence and branches to one of many possible services routines. The particular service routine reached belongs to the highest-priority device among all devices interrupted the computer. The drawback of the software method is that, the time required to poll them can exceed the time available to service the I/O device, if there are many interrupts. In this situation a hardware priority-interrupt can be used to speed up the operation.
A hardware priority-interrupt unit functions as an overall manager in an interrupt system environment. Each interrupt source has its own interrupt vector to access its own service routine directly, to speed up the operation. The hardware priority function can be established by either a serial or a parallel connection of interrupt lines. The serial connection is also known as the daisy-chaining method.
Daisy-chaining Priority : The daisy-chaining method of establishing priority consists of a serial connection of all devices that request an interrupt. The device with the highest priority is placed in the first position, followed by lower-priority devices upto the device with the lowest priority, which is placed last in the chain. The following figure demonstrate the method of connection between three devices and the CPU.
The interrupt request line is common to all devices and forms a wired logic connection. If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU. The interrupt line stays in the high-level state and no interrupts are recognized by the CPU, only when no interrupts are pending. And is equivalent to a negative logic or operation. The CPU responds to an interrupt request by enabling the interrupt acknowledge line.
This signal is received by device 1 at its PI(priority in) input. The acknowledge signal passes on the next device through the PO(Priority Out) Output only if device 1 is not requesting an interrupt. It blocks the acknowledgement signal from the next device by placing a 0 in the PO output, if device I has a pending interrupt. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the CPU to use, during the interrupt cycle.
A device with a 0 in its PI input generate a O in its PO output to inform the next-lower-priority device that the acknowledge signal has been blocked. A device that is requesting an interrupt and has a 1 in its PI input will intercept the acknowledge signal by placing a O in its PO output. It transmits the acknowledge signal to the next device by placing in 1 in its PC Output, if the device does not have pending interrupts.
Thus the device with PI = 1 and PO = 0 is the one with the highest priority that is requesting an interrupt, and this device places its vector address (VAD) on the data bus. The daisy chain arrangement gives the highest priority to the device that receives the interrupt acknowledge signal from the CPU. The farther the device is from the first position; the lower is its priority.
Parallel Priority Interrupt: The parallel priority interrupt method uses a register whose bits are set separately by the interrupt signal from each device. Priority is established according to the position of the bits in the register. The circuit may include a mask register whose purpose is to control the status of each interrupt request in addition to the interrupt register. The mask register can be programmed to disable lower-priority interrupts while a higher priority device is being serviced. It also provides a facility that allows a high priority device to interrupt the CPU while a lower-priority device is being serviced.
The Priority logic for a system of four interrupt sources is demonstrated in the previous figure. It consists of an interrupt register whose individual bits are set by external conditions and cleared by program instructions. The magnetic disk being a high-speed device, is given the highest priority. The printer has the next priority followed by a character reader and a keyboard. The mask register has the same number of bits as the interrupt register.
By means of program instructions, it is possible to set or reset any bit in the mask register. Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four inputs to a priority encoder. In this way an interrupt is recognized only if its corresponding mask bit is set to 1 by the program. The priority encoder generates two bits of the vector address, which is transferred to the CPU.
Another output from the encoder sets an interrupt status flip-flop IST when an interrupt that is not masked occurs. The interrupt enable flip-flop IEN can be set or cleared by the program to provide an overall control over the interrupt system. The output of IST ANDed with IEN provide a common interrupt signal for the CPU. The interrupt acknowledge INTACK signal from the CPU enables the bus buffers in the output register and a vector address VAD is placed into the data bus
Ans : The program enters a wait loop in which it repeatedly tests the device status. During this period, the processor is not performing any useful computation. There are many situations where other tasks can be performed while waiting for an I/O device to become ready. To allow this to happen, we can arrange for the I/O device to alert the processor when it becomes ready. It can do so by sending a hardware signal called an interrupt to the processor.
Priority Interrupt: A priority interrupt is a system that establishes a priority over the various sources to determine the condition which is to be serviced first, when two or more requests arrive simultaneously.
The system may also determine which conditions are permitted to interrupt the computer while another interrupt is being serviced. Higher priority interrupt levels are assigned to requests which, if delay or interrupted, could have serious consequences. When two devices interrupt the computer at the same time, the computer services the device, with the higher priority first.
Establishing the priority of simultaneous interrupts can be done by software or hardware. A polling procedure is used to identify the highest priority source by software means. In this method there is one common branch addresses for all interrupts the Program that takes care of interrupts begins of the branch address and polls the interrupt sources in sequence. The order in which they are tested determines the priority of each interrupt.
The initial service routine for all interrupts consists of a program that tests the interrupt sources in sequence and branches to one of many possible services routines. The particular service routine reached belongs to the highest-priority device among all devices interrupted the computer. The drawback of the software method is that, the time required to poll them can exceed the time available to service the I/O device, if there are many interrupts. In this situation a hardware priority-interrupt can be used to speed up the operation.
A hardware priority-interrupt unit functions as an overall manager in an interrupt system environment. Each interrupt source has its own interrupt vector to access its own service routine directly, to speed up the operation. The hardware priority function can be established by either a serial or a parallel connection of interrupt lines. The serial connection is also known as the daisy-chaining method.
Daisy-chaining Priority : The daisy-chaining method of establishing priority consists of a serial connection of all devices that request an interrupt. The device with the highest priority is placed in the first position, followed by lower-priority devices upto the device with the lowest priority, which is placed last in the chain. The following figure demonstrate the method of connection between three devices and the CPU.
The interrupt request line is common to all devices and forms a wired logic connection. If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU. The interrupt line stays in the high-level state and no interrupts are recognized by the CPU, only when no interrupts are pending. And is equivalent to a negative logic or operation. The CPU responds to an interrupt request by enabling the interrupt acknowledge line.
This signal is received by device 1 at its PI(priority in) input. The acknowledge signal passes on the next device through the PO(Priority Out) Output only if device 1 is not requesting an interrupt. It blocks the acknowledgement signal from the next device by placing a 0 in the PO output, if device I has a pending interrupt. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the CPU to use, during the interrupt cycle.
A device with a 0 in its PI input generate a O in its PO output to inform the next-lower-priority device that the acknowledge signal has been blocked. A device that is requesting an interrupt and has a 1 in its PI input will intercept the acknowledge signal by placing a O in its PO output. It transmits the acknowledge signal to the next device by placing in 1 in its PC Output, if the device does not have pending interrupts.
Thus the device with PI = 1 and PO = 0 is the one with the highest priority that is requesting an interrupt, and this device places its vector address (VAD) on the data bus. The daisy chain arrangement gives the highest priority to the device that receives the interrupt acknowledge signal from the CPU. The farther the device is from the first position; the lower is its priority.
Parallel Priority Interrupt: The parallel priority interrupt method uses a register whose bits are set separately by the interrupt signal from each device. Priority is established according to the position of the bits in the register. The circuit may include a mask register whose purpose is to control the status of each interrupt request in addition to the interrupt register. The mask register can be programmed to disable lower-priority interrupts while a higher priority device is being serviced. It also provides a facility that allows a high priority device to interrupt the CPU while a lower-priority device is being serviced.
The Priority logic for a system of four interrupt sources is demonstrated in the previous figure. It consists of an interrupt register whose individual bits are set by external conditions and cleared by program instructions. The magnetic disk being a high-speed device, is given the highest priority. The printer has the next priority followed by a character reader and a keyboard. The mask register has the same number of bits as the interrupt register.
By means of program instructions, it is possible to set or reset any bit in the mask register. Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four inputs to a priority encoder. In this way an interrupt is recognized only if its corresponding mask bit is set to 1 by the program. The priority encoder generates two bits of the vector address, which is transferred to the CPU.
Another output from the encoder sets an interrupt status flip-flop IST when an interrupt that is not masked occurs. The interrupt enable flip-flop IEN can be set or cleared by the program to provide an overall control over the interrupt system. The output of IST ANDed with IEN provide a common interrupt signal for the CPU. The interrupt acknowledge INTACK signal from the CPU enables the bus buffers in the output register and a vector address VAD is placed into the data bus
Assign-3
1Q : Explain about Synchronous Bus and Asynchronous Bus?
2Q : Explain about Standard I/O Interfaces ?
3Q : Explain about PCI Bus ?
4Q : Explain about SCSI Bus?
5Q : Explain about Universal Serial Bus ?
6Q : Differenciate Parallel and Serial I/O Interfaces?
7Q : Discuss I/O Versus Memory Bus?
8Q : Explain in detail about different modes of transfers?
9Q : What is priority interrupt ? Explain Daisy chain interrupt and
parallel priotity interrupt system with necessary diagrams
10Q : Explain indetail about Addition and Subtraction of Signed Numbers ?
2Q : Explain about Standard I/O Interfaces ?
3Q : Explain about PCI Bus ?
4Q : Explain about SCSI Bus?
5Q : Explain about Universal Serial Bus ?
6Q : Differenciate Parallel and Serial I/O Interfaces?
7Q : Discuss I/O Versus Memory Bus?
8Q : Explain in detail about different modes of transfers?
9Q : What is priority interrupt ? Explain Daisy chain interrupt and
parallel priotity interrupt system with necessary diagrams
10Q : Explain indetail about Addition and Subtraction of Signed Numbers ?
I/O
1. What is input –output interface? Discuss different types of interfaces?
Input-Output Interface: Input-Output Interface provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. The purpose of the communication link is to resolve the differences that exist between the central computer and each peripheral. Data transfer rate of systems include special hardware components between the CPU and peripherals to supervise and synchronize all input transfers. These components are called interface units because they interface between the processor bus and the peripheral device.
There are basically 2 types of interfaces. 1) Parallel Interface 2) Serial Interface
In Parallel interface, there are multiple lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously that is all the bits of a word are transferred simultaneously over the data bus. In serial interface there is only one line used to transmit data and bits are transmitted one at a time. A parallel Interface is commonly used for higher-speed peripherals. Like tape and disk where as serial is used for printer and terminals
In addition, each device may have its own controller that supervises the operations of the particular mechanism in the peripheral.
I/O Bus and Interface Modules: A typical communication link between the processor and several peripherals is designed in order to attain a full fledged communication between them. The I/O bus consists data lines, address lines and control lines. The magnetic disk, printer, and terminal are employed in particularly any general purpose computer. The magnetic tape is used in some computers for backup storage. Each peripherals device has associated with it an interface unit. A controller may be housed separately or may be physically integrated with the peripheral. The I/O bus from the processor is attached to all peripheral interfaces.
To communicate with a particular device, the processor places a device address on the address lines. A interface unit is associated with each peripheral device and its function is to decode the address lines and find out whether the address belongs to that device. Once the interface decodes the signal on the address lines and identifies that the address belongs to the peripheral associated with the interface, the peripheral device is switched on. Each peripheral has controller associated with the device. Like, if the output device is a printer, the printer controller controls the movement of paper, aligning in the proper place and selecting the printing characters to be printed. A peripheral controller is either integrated with the device or housed as part of the device. Once the control is set properly, data may be transferred from the CPU to peripheral device or vice versa through data lines. Below figure shows the Interfacing CPU to Peripheral devices.
2Q : Discuss I/O versus Memory Bus
I/O Versus Memory Bus: Processor should communicate with both I/O and memory unit like the I/O bus, the memory bus contain data, address, and read/write control lines. There are three ways that computer buses can be used to communicate with memory and I/O.
1. Use two separate buses, one for memory and the other for I/O
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control lines.
In first method, the computer has independent sets of data, address and control buses, one for accessing memory and the other for I/O. And it is done in computers which provide a separate I/O processor (I/O processor) in addition to the central processing unit (CPU). The memory communicates with both the CPU and the I/O processor through a memory bus. The I/O processor communicates with both the CPU and I/O processor through a memory bus. The I/O processor also communicates with the input and output devices through a separate I/O bus with its own address, data and control lines. The purpose of the I/O processor is to provide an independent pathway for the transfer of information between external devices and internal memory. The I/O processor is sometime also known as data channel.
3Q. Differentiate between memory mapped and isolated I/O
Ans : Many computers use on common bus to transfer information between memory or I/O and the CPU. The distinction between a memory transfer and I/O transfer is made through separate read and write lines. The CPU specifies whether the address on the address lines is for a memory word of for an interface register by enabling one of two possible read or write lines. This configuration isolates all I/O interface address from the address assigned to memory and is referred to as the isolated I/O method for assigning address in a common bus.
Isolated I/O : Isolated I/O is a configuration maintaining independent set of input and output instructions. The central processing unit receives the opcode of a given instruction, decodes it and transmits the address of the given peripheral device on the common address lines shared by processor, memory and other I/O peripherals. Therefore, CPU performs the derived operation that is either I/O read or I/O write control lines.
Memory mapped I/O : The CPU maintains common address space for both units that is memory as well as I/O Unit. Therefore, the CPU utilizes the registers such as data and status registers which belongs to I/O Units as a memory space for storing various addresses.
4Q. Explain in detail about different modes of transfers:
Ans : Modes of Transfer : The CPU merely executes the I/O instructions and may accept the data temporarily, but the ultimate source or destination is the memory unit. Data transfer between the central computer and I/O devices may be handled in a variety of modes. Data transfer to and from peripherals may be handled in one of the three possible modes:
1) Programmed I/O
2) Interrupt Driven I/O
3) Direct memory access (DMA)
Programmed I/O : In Programmed I/O approach, the transfer of data item is initiated by an instruction in the computer program. The data transfer in between a CPU register and ( a register in the ) peripheral and is useful in low speed computer systems to minimize hardware costs. The data is transferred between a register in CPU and another (buffer) register in the peripheral. For example, IN and OUT instructions in 8085 processor for performing data transfer between accumulator and a register in the peripheral devices. Some more instructions may be required to transfer the data into memory from accumulator on the CPU side and between the buffer ends into the appropriate location in the peripheral device.
A constant monitoring of the peripheral by CPU is required to transfer data under program control. The CPU is required to monitor the interface of the peripheral device to find out when and additional data transfer takes place. The instructions executed in CPU monitor the various registers to ensure that data transfer takes place smoothly without any overriding of data items or loss of data items. The CPU must stay in the program loop until the I/O interfacing unit informs that it is ready for data transfer to take place. And this mechanism keeps the processor busy for a very long time.
Interrupt-Driven I/O : Interrupt Driven I/O approach of data transfer reduces the requirements on processor time as compared to the programmed approach to input and output data transfer. An interrupt is used to indicate to the CPU that it is ready to accept data for transfer from CPU or a data item is available for transfer, CPU executes another program and therefore the demand on CPU time is reduced. During the period CPU is executing other programs, I/O interface monitors continually the external device and generates an interrupt signal (request) to the computer. CPU suspends the present task and branches to an interrupt service routine. When an interrupt signal is detected.
The interrupt service routine, which indicates the action required, is executed and at the end of the execution of interrupt service routine, CPU returns to the program that it was originally executing. The interruption of CPU Program is planned at the beginning of fetching any instruction, the system checks from any interrupt Driven I/O and programmed I/O are useful when the amount of data required to be transferred is small. Only one byte or word can be transferred each time. If large volumes of data are required to be transferred another approach is used.
Direct Memory Access: (DMA)
The Direct Memory Access is used for the transferring large volumes of data between main memory and a peripheral device through the memory bus. In the DMA approach the CPU initiates the data transfer by supplying the interface, the starting address of the data and the number of words of data the execution of other instructions. During DMA period, CPU will not be able to access memory to execute other instructions. The CPU allows the memory use to be controlled by IO data transfer during DMA operations. At the end of DMA operations. The CPU has to delay all memory access operations during direct memory – I/O transfer are much less frequent than processor to memory access operations.
Many computer systems use an I/O processor which combined the interface logic with direct memory access operations. A large number of peripheral devices can be handled by an I/O processor with the help of interrupts and DMA facility. Such computer system can be treated as serving three separate modules. A memory unit, CPU and an I/O Processor.
Input-Output Interface: Input-Output Interface provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. The purpose of the communication link is to resolve the differences that exist between the central computer and each peripheral. Data transfer rate of systems include special hardware components between the CPU and peripherals to supervise and synchronize all input transfers. These components are called interface units because they interface between the processor bus and the peripheral device.
There are basically 2 types of interfaces. 1) Parallel Interface 2) Serial Interface
In Parallel interface, there are multiple lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously that is all the bits of a word are transferred simultaneously over the data bus. In serial interface there is only one line used to transmit data and bits are transmitted one at a time. A parallel Interface is commonly used for higher-speed peripherals. Like tape and disk where as serial is used for printer and terminals
In addition, each device may have its own controller that supervises the operations of the particular mechanism in the peripheral.
I/O Bus and Interface Modules: A typical communication link between the processor and several peripherals is designed in order to attain a full fledged communication between them. The I/O bus consists data lines, address lines and control lines. The magnetic disk, printer, and terminal are employed in particularly any general purpose computer. The magnetic tape is used in some computers for backup storage. Each peripherals device has associated with it an interface unit. A controller may be housed separately or may be physically integrated with the peripheral. The I/O bus from the processor is attached to all peripheral interfaces.
To communicate with a particular device, the processor places a device address on the address lines. A interface unit is associated with each peripheral device and its function is to decode the address lines and find out whether the address belongs to that device. Once the interface decodes the signal on the address lines and identifies that the address belongs to the peripheral associated with the interface, the peripheral device is switched on. Each peripheral has controller associated with the device. Like, if the output device is a printer, the printer controller controls the movement of paper, aligning in the proper place and selecting the printing characters to be printed. A peripheral controller is either integrated with the device or housed as part of the device. Once the control is set properly, data may be transferred from the CPU to peripheral device or vice versa through data lines. Below figure shows the Interfacing CPU to Peripheral devices.
2Q : Discuss I/O versus Memory Bus
I/O Versus Memory Bus: Processor should communicate with both I/O and memory unit like the I/O bus, the memory bus contain data, address, and read/write control lines. There are three ways that computer buses can be used to communicate with memory and I/O.
1. Use two separate buses, one for memory and the other for I/O
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control lines.
In first method, the computer has independent sets of data, address and control buses, one for accessing memory and the other for I/O. And it is done in computers which provide a separate I/O processor (I/O processor) in addition to the central processing unit (CPU). The memory communicates with both the CPU and the I/O processor through a memory bus. The I/O processor communicates with both the CPU and I/O processor through a memory bus. The I/O processor also communicates with the input and output devices through a separate I/O bus with its own address, data and control lines. The purpose of the I/O processor is to provide an independent pathway for the transfer of information between external devices and internal memory. The I/O processor is sometime also known as data channel.
3Q. Differentiate between memory mapped and isolated I/O
Ans : Many computers use on common bus to transfer information between memory or I/O and the CPU. The distinction between a memory transfer and I/O transfer is made through separate read and write lines. The CPU specifies whether the address on the address lines is for a memory word of for an interface register by enabling one of two possible read or write lines. This configuration isolates all I/O interface address from the address assigned to memory and is referred to as the isolated I/O method for assigning address in a common bus.
Isolated I/O : Isolated I/O is a configuration maintaining independent set of input and output instructions. The central processing unit receives the opcode of a given instruction, decodes it and transmits the address of the given peripheral device on the common address lines shared by processor, memory and other I/O peripherals. Therefore, CPU performs the derived operation that is either I/O read or I/O write control lines.
Memory mapped I/O : The CPU maintains common address space for both units that is memory as well as I/O Unit. Therefore, the CPU utilizes the registers such as data and status registers which belongs to I/O Units as a memory space for storing various addresses.
4Q. Explain in detail about different modes of transfers:
Ans : Modes of Transfer : The CPU merely executes the I/O instructions and may accept the data temporarily, but the ultimate source or destination is the memory unit. Data transfer between the central computer and I/O devices may be handled in a variety of modes. Data transfer to and from peripherals may be handled in one of the three possible modes:
1) Programmed I/O
2) Interrupt Driven I/O
3) Direct memory access (DMA)
Programmed I/O : In Programmed I/O approach, the transfer of data item is initiated by an instruction in the computer program. The data transfer in between a CPU register and ( a register in the ) peripheral and is useful in low speed computer systems to minimize hardware costs. The data is transferred between a register in CPU and another (buffer) register in the peripheral. For example, IN and OUT instructions in 8085 processor for performing data transfer between accumulator and a register in the peripheral devices. Some more instructions may be required to transfer the data into memory from accumulator on the CPU side and between the buffer ends into the appropriate location in the peripheral device.
A constant monitoring of the peripheral by CPU is required to transfer data under program control. The CPU is required to monitor the interface of the peripheral device to find out when and additional data transfer takes place. The instructions executed in CPU monitor the various registers to ensure that data transfer takes place smoothly without any overriding of data items or loss of data items. The CPU must stay in the program loop until the I/O interfacing unit informs that it is ready for data transfer to take place. And this mechanism keeps the processor busy for a very long time.
Interrupt-Driven I/O : Interrupt Driven I/O approach of data transfer reduces the requirements on processor time as compared to the programmed approach to input and output data transfer. An interrupt is used to indicate to the CPU that it is ready to accept data for transfer from CPU or a data item is available for transfer, CPU executes another program and therefore the demand on CPU time is reduced. During the period CPU is executing other programs, I/O interface monitors continually the external device and generates an interrupt signal (request) to the computer. CPU suspends the present task and branches to an interrupt service routine. When an interrupt signal is detected.
The interrupt service routine, which indicates the action required, is executed and at the end of the execution of interrupt service routine, CPU returns to the program that it was originally executing. The interruption of CPU Program is planned at the beginning of fetching any instruction, the system checks from any interrupt Driven I/O and programmed I/O are useful when the amount of data required to be transferred is small. Only one byte or word can be transferred each time. If large volumes of data are required to be transferred another approach is used.
Direct Memory Access: (DMA)
The Direct Memory Access is used for the transferring large volumes of data between main memory and a peripheral device through the memory bus. In the DMA approach the CPU initiates the data transfer by supplying the interface, the starting address of the data and the number of words of data the execution of other instructions. During DMA period, CPU will not be able to access memory to execute other instructions. The CPU allows the memory use to be controlled by IO data transfer during DMA operations. At the end of DMA operations. The CPU has to delay all memory access operations during direct memory – I/O transfer are much less frequent than processor to memory access operations.
Many computer systems use an I/O processor which combined the interface logic with direct memory access operations. A large number of peripheral devices can be handled by an I/O processor with the help of interrupts and DMA facility. Such computer system can be treated as serving three separate modules. A memory unit, CPU and an I/O Processor.