new Q

Briefly Explain the following:-
1)Micro Operation :- The Operations executed on data stored in registers are called micro operations. A micro operation is an elementary operation performed on the Information stored in one or more registers. The result of the operation may replace the previous binary information of a register or may transfer to another register. A micro operation is an elementary operation performed with the data stored in registers. The micro operations most often encountered in digital computers are classified into four categories:
1. Register transfer microoperations transfer binary information from one register to another
2. Arithmetic microoperations perform arithmetic operations on numeric data stored in registers
3. Logic microoperations perform bit manipulation operations on nonnumeric data stored in registers
4. Shift microoperations perform shift operations on data stored in registers.
2) Page Replacement : - A virtual memory system is a combination of shardware and software techniques. The memory management software system handles all the software operations for the efficient utilization of memory space. It must decide:
1) which page in main memory ought to be removed to make room for a new page.
2)When a new page is to be transferred from auxiliarly memory to main memory.
3) Where the page is to be placed in main memory
3) Page Fault : When a program starts execution, one or more pages are transferred into main memory and the page table is set to indicate their position. The program is executed from main memory until it attempts to reference a page that is still in auxiliary memory. This condition is called page fault when page fault occurs, the execution of the present program is suspended until the required page is brought into main memory.
4)Replacement Algorithms:• When a new block is to be brought into the cache and all the positions that it may occupy are full, the cache controller must decide which of the old blocks to overwrite. In a direct mapped cache, the position of each blocks is predetermined, therefore, no replacement strategy required. But in associative and set associative caches there exists some flexibility.
• In general, the aim is to keep blocks in the cache that are likely to be referenced but determining which blocks are about to be referenced is difficult . since programs usually resides in localized areas for reasonable periods of time, there is a high probability that blocks that have been referenced recently will be referenced again.
• When a block is to be overwritten, it is easy to overwrite the one that has gone the longest time without being referenced. This block is called the least recently used block and the technique is called the least recently used replacement algorithm.
• To perform Least recently used function, the cache controller must record references to all blocks as computation progresses.
For Example: It is required to record the Least Recently Used blocks of four-blocks set in a set-associative cache. A 2-bit counter can be used for each block. When a hit occurs, the counter of the block that is referenced is set to 0. Counters with values originally lower than the referenced one are incremented by one, and all others remain unchanged.
• When a miss occurs and the set is not full, the counter associated with the new block loaded from the main memory is set to 0, and the values of all other counters are increased by one. When a miss occurs and the set is full, the block with the counter value 3 is removed, the new block is put in its place, and its counter is set to 0. The other three block counters are incremented by one. It can be easily verified that the counter values of occupied blocks are always distinct.
• The Least Recently Used algorithm has been used extensively. Although it performs well for many access patterns, it can lead to poor performance in some cases. Performance of the Least Recently Used algorithm can be improved by introducing a small amount of randomness in deciding which block to replace.
5. Advantages of using Virtual Memory • Virtual memory is the separation of user logical memory from physical memory. This separation allows an extremely large virtual memory to be provided for programmers when only a smaller physical memory is available.
• Virtual memory makes the task of programming much easier, because the programs no longer needs to worry about the amount of physical memory available or about what code can be placed in overlays , but can concentrate instead on the problem to be programmed.
• On system which support virtual memory, overlays have virtually disappeared.
• Virtual memory is commonly implemented by demand paging. It can also be implemented in a segmentation system with several systems provided a paged segmentation scheme, where segments are broken into pages. Demand segmentation can also be used to provide virtual memory.
• To free user from the need to carry out storage reallocation and permit the efficient sharing of available memory space by different users.
• To make the program independent of the configuration and capacity of the physical memory for execution.
• To achieve the very low cost per bit and low access time that are possible with memory hierarchy.
6. Vectored Interrupts :
There are two possible implementations of the vectored interrupts depending on the type of microprocessor.
1) Vector address is Fixed
• Here, the interrupt request coming from I/O devices are stored in interrupt register by setting the corresponding bits.
• The interrupt mask register is user programmable which is used to disable/mask corresponding interrupt requests.
• When multiple interrupts are forwarded to the input of priority encoder, it will encode only higher priority interrupt input using priority encoder and accordingly code will be generated. This code is inserted at predefined locations in program counter(PC)
• This defines the vector location for the interrupt, interrupt request is sent to the processor from priority encoder.
2) Vector address given by the I/O device• The system is implemented in multi level interrupt where separate interrupt request line(IRQ) and their acknowledge (ACK) are used for each of the I/O device.
• When multiple interrupt requests come from multiple I/O devices then priority control logic will resolve the priority and will send common interrupt request to the CPU.
• CPU sends interrupt acknowledge to the priority control logic, which in turn gives acknowledgement to the higher priority interrupting device.
7. Bus Arbitration : Bus systems with more than one potential bus master need a bus arbitration mechanism to allocate the bus to a bus master. Although the CPU is the bus master most of the time, the DMA controller acts as the bus master during certain I/O transfers. In principle, bus arbitration can be done either statically or dynamically
Static bus arbitration : In static bus arbitration, bus allocation among the masters is done in a predetermined way. For example, we might use a round-robin allocation that rotates the bus among the masters. The main advantage of a static mechanism is that it is easy to implement. How ever, since bus allocation follows a predetermined pattern rather than the actual need, a master may be given the bus even if it does not need it. This kind of allocation leads to inefficient use of the bus. Consequently, most implementations use a dynamic bus arbitration, which uses a demand-driven allocation scheme.
Dynamic Bus arbitration : In dynamic bus arbitration, bus allocation is done in response to a request from a bus master. To implement dynamic arbitration, each master should have a bus request and grant lines. A bus master uses the bus request line to let others know that it needs to bus to perform a bus transaction. Before it can initiate the bus transaction, it should receive permission to use the bus via the bus grant line. Dynamic arbitration consists of bus allocation and release policies.
Bus arbitration can be implemented in one of two basic ways : Centreaized or distributed.
In Centralized scheme, a central arbiter receives bus requests from all masters. The arbiter using the bus allocation policy in effect, determines which bus request should be granted. This decision is conveyed through the bus grant lines. Once the transaction is over, the master holding the bus would release the bus; the release policy determines the actual release mechanism.
In the Distributed implementation, arbitration hardware is distributed among the masters. A distributed algorithm is used to determine the master that should get the bus.
8. Bus Design Issues :
• Bus width : Bus width refers to the data and address bus widths, System performance improves with a wider data bus as we can move more bytes in parallel. We increase the addressing capacity of the system by adding more address lines.
• Bus Type : There are two types of buses: dedicated and multiplexed
• Bus Operations : Bus systems support several types of operations to transfer data. These include the read, write, block transfer, read-modify-write, and interrupt.
• Bus Arbitration : Bus arbitration can be done in one of two ways : Centralized or distributed.
• Bus Timing : As mentioned in the last section, buses can be designed as either synchronous or asynchronous.
9. Explain BIOS and CMOS
BIOS Means Basic Input /Output Services, To communicate with different devices of computer and different parts of motherboard, the processor goes to the ROM chip to access the proper program. Understand that there are many programs on the ROM chip. To communicate with the basic hardware it requires hundred of little programs (2 to 30 lines of code each). These hundreds of little programs stored on the ROM chip are called, collectively, the BIOS, each tiny program is called a service.
CMOS means Complementary Metal-Oxide Semiconductor , the BIOS information that can change will be stored in special RAM chip is called CMOS chip . So CMOS must be changed when you make certain hardware changes, you need to able to access and update the data on the CMOS chip. This function is called CMOS setup program. CMOS setup is a special program that allows you to make changes on the CMOS chip. It is stored on the System ROM. There are many ways to start CMOS setup program, depending on the brand of BIOS you have on your computer.
10. Interrupt Nesting
The device raises an interrupt request, The processor interrupts the program currently being executed. The interrupts should be disabled during the execution of an interrupt-service routine, to ensure that a request from one device will not cause more than one interruption. The same arrangement is often used when several devices are involved, in which case execution of a given interrupt-service routine, once started, always continues to completion before the processor accepts an interrupt request from a second device.

q1.f

Explain in detail about virtual memories and Address translation scheme.
A simple method for translating virtual addresses into physical addresses is to assume that all programs and data are composed of fixed-length units called pages. Each of which consists of a block of words that occupy contiguous locations in the main memory. Pages commonly range from 2k to 16k bytes in length. They constitute the basic unit of information that is moved between the main memory and the disk whenever the translation mechanism determines that a move is required. Pages should not be too small, because the access time of a magnetic disk is much longer than the access time of the main memory. The reason for this is that it takes a considerable amount of time to locate the data on the disk, but once located, the data can be transferred at a rate of several megabytes per second. On the other hand, if pages are too large it is possible that a substantial portion of a page may not be used, yet this unnecessary data will occupy valuable space in the main memory.
The cache bridges the speed gap between the processor and the main memory and is implemented in hardware. The virtual-memory mechanism bridges the size and speed gaps between the main memory and secondary storage and is usually implemented in part by software techniques. Conceptually, cache techniques and virtual memory techniques are very similar. They differ mainly in the details of the implementation.
A virtual memory address translation method based on the concept of fixed-length pages. Each virtual address generated by the processor, whether it is for an instruction fetch or an operand fetch/ store operation, is interpreted as a virtual page number(high ordered bits) followed by an offset(low ordered bits) that specifies the location of a particular byte(or word) within a page. Information about the main memory location of each page is kept in a page table. This information includes the main memory address where the page is stored and the current status of the page. An area in the main memory that can hold one page is called page frame. The starting address of the page table is kept in a page table base register. By adding the virtual page number to the contents of this register, the address of the corresponding entry in the page table is obtained. The contents of this location give the starting address of the page if that page currently resides in the main memory.
Each entry in the page table also includes some control bits that describe the status of the page while it is in the main memory. One bit indicates the validity of the page, that is, whether the page is actually loaded in the main memory, this bit allows the operating system to invalidate the page without actually removing it. Another bit indicates whether the page has been modified during its residency in the memory. As in cache memories this information is needed to determine whether the page should be written back to the disk before it is removed from the main memory to make room for another page. Other control bits indicate various restrictions that may be imposed on accessing the page. For example, a program may be given full read and written permission, or it may be restricted to read accesses only.

q1.e

3. Explain any two mapping procedures in cache memory
Direct Mapping: Direct mapping is used for random access memory since associative memories are not economical and added associative logic with each cell. The following figures demonstrates the direct mapping.
The CPU address of 15-bits is divided into two fields. The nine least significant bits forms the index field and the remaining six bits form the Tag field. From the above figure, main memory requires and address that includes both the tag and the index bits. The number of bits in the field is equal to the number of address bits required to access the cache memory.
Generally these are 2K words in cache memory and 2n words in main memory. The n-bit memory address is divided into index and tag field. K-bit for index field and (n-k) bits for tag field. The cache with direct mapping uses n-bits address to access main memory organization of the words and cache consists of the data word and it’s associated tag only when a new word is first brought into the cache, the tag bits are stored alongside the data bits.
When CPU generates a memory request, the index field is used for the address to access the cache. The tag field of the CPU address is compared with the word read from the cache. If the two tags match, ahit is produced and the required data word is in cache. If there is no match, there is a miss and the desired data word is read from the main memory.
It is then stored in the cache together with new tag replaced by the previous value. The disadvantage of direct mapping is the hit ratio drop if two or more words whose addresses have the same index but different tags are accessed repeatedly. However this can be minimized by the fast technique, such that words are relatively for a part in the address range 512 location are here in this example.

Consider a numerical example to know how the direct mapping operates. The word 1220 is stored at address 00 000 in the main memory, and the same address is stored in the cache as index = 000, tag=00, data = 1220. If CPU wants to access the word stored at address 02000(word =5670). The index address is 000, so it is used to access the cache. The two tags are compared. The cache tag is 00 but the address tag is 02, which does not produce a match. Therefore the main memory is accessed and the data word 5670 is transferred to the CPU. The cache word at index address 000 is then replaced with a tag of 02 and data of 5670.

The above figure shows Direct Mapping Cache organization
The direct –Mapping is expressed as i=j modulo m
Where, i= Cache line number, j=Main memory block number, n=Number of lines of Cache memory.
Set Associative Mapping : The main draw back of direct mapping is two words with same index address but different values cannot reside in cache memory at the same time.
Therefore an improved cache organization implemented called as set associative mapping. And is used to store two or more words of memory under the same index address. Each data word is stored together with its tag and the number of tag-data pairs in one word of cache is called a set.
For example, consider a set associative cache organization for a set size of two as shown in figure, Each tag requires six bits and each data word has 12 bits, therefore word length becomes 2(6+12) = 36 bits. An index address of a bits can accomadate 1024 words of main memory since each word of cache contains two data word.
In general, a set-associative cache of set size k will accomadate k words main memory.


The octal numbers listed in figure are with reference to the main memory contents. The words stored at addresses 01000 and 02000 of main memory are stored in cache memory at index address 000. Similarly, the words stored at addresses 02777 and 00777 are stored in at index address 777 of cache memory.
As the CPU generates a memory request, the index address is used to access the cache. The tag field of the CPU address is then compared with both tags of the cache to see if a match occurs. The comparison is done by an associative search of the tags in the set similar to an associative memory search. Thus the name “Set associative”.
At the set size increases, bit ration also increases because more words, with same index address but different tags can be stored in cache. However as set size increases and requires complex comparision logic.
The relationship are m = v * k
i = j MODULO V
Where i = Cache Set number
j = main memory block number
m = number of lines in the cache.

q1.d

f) Associative Mapping : If the active portions of the program and data are placed in a fast small memory to reduce the average memory access time. Such a fast small memory is referred as Cache memory. Fast access time is the feature of cache memory. Thus the process of transferring of data from main memory to cache is referred as mapping function, The Associative Mapping is used for fastest and flexible cache organization. Below figure demonstrates the associative mapping. The Associative memory stores both content (data) and address of the memory word. Let us consider that three words currently stored in the cache.

The address value of 15-bits is shown as five digit octal number and its corresponding 12-bit word as a four digit octal number. A CPU address and the associative memory is searched for matching address. If the address is found, the relevant(corresponding) 12-bit data is read and send to the CPU. If the address is not found then main memory is accessed for the word and hence address-data pair is transferred to the associative cache memory.
In case, if the cache is full and cannot hold address-data pair of main memory, a room is formed for a pair that is needed and not present in the cache. The decision about which pair should be replaced can be determined form the replacement algorithm. Whenever a new word is requested by main memory, a first-in-first-out(FIFO) replacement policy is used.

q1.c

Explain in detail about virtual memories and Address translation scheme.
A simple method for translating virtual addresses into physical addresses is to assume that all programs and data are composed of fixed-length units called pages. Each of which consists of a block of words that occupy contiguous locations in the main memory. Pages commonly range from 2k to 16k bytes in length. They constitute the basic unit of information that is moved between the main memory and the disk whenever the translation mechanism determines that a move is required. Pages should not be too small, because the access time of a magnetic disk is much longer than the access time of the main memory. The reason for this is that it takes a considerable amount of time to locate the data on the disk, but once located, the data can be transferred at a rate of several megabytes per second. On the other hand, if pages are too large it is possible that a substantial portion of a page may not be used, yet this unnecessary data will occupy valuable space in the main memory.
The cache bridges the speed gap between the processor and the main memory and is implemented in hardware. The virtual-memory mechanism bridges the size and speed gaps between the main memory and secondary storage and is usually implemented in part by software techniques. Conceptually, cache techniques and virtual memory techniques are very similar. They differ mainly in the details of the implementation.
A virtual memory address translation method based on the concept of fixed-length pages. Each virtual address generated by the processor, whether it is for an instruction fetch or an operand fetch/ store operation, is interpreted as a virtual page number(high ordered bits) followed by an offset(low ordered bits) that specifies the location of a particular byte(or word) within a page. Information about the main memory location of each page is kept in a page table. This information includes the main memory address where the page is stored and the current status of the page. An area in the main memory that can hold one page is called page frame. The starting address of the page table is kept in a page table base register. By adding the virtual page number to the contents of this register, the address of the corresponding entry in the page table is obtained. The contents of this location give the starting address of the page if that page currently resides in the main memory.
Each entry in the page table also includes some control bits that describe the status of the page while it is in the main memory. One bit indicates the validity of the page, that is, whether the page is actually loaded in the main memory, this bit allows the operating system to invalidate the page without actually removing it. Another bit indicates whether the page has been modified during its residency in the memory. As in cache memories this information is needed to determine whether the page should be written back to the disk before it is removed from the main memory to make room for another page. Other control bits indicate various restrictions that may be imposed on accessing the page. For example, a program may be given full read and written permission, or it may be restricted to read accesses only.

q1.b

2Q. Explain the Single and multiple Bus Organization of C.P.U
A group of lines that serves as a connecting path for several devices is called bus. In addition to the lines that carry the data, the bus must have lines for address and control purposes. The simplest way to interconnect functional units is to use a single bus, all units are connected to bus, because the bus used for only one transfer at a time, only two units can actively use the bus at any given time. Bus control lines are used to arbitrate multiple requests for use of the bus. The main virtue of the single-bus structure is its low cost and its flexibility for attaching peripheral devices. Systems that contain multiple buses achieve more concurrency in operations by allowing two or more transfers to be carried out at the same time. This leads to better performance but at an increased cost. The devices connected to a bus vary widely in their speed of operation. Some electromechanical devices, such as keyboards and printers, are relatively slow. Others like magnetic or optical disks, are considerably faster. Memory and processor units operate at electronic speeds, making them the fastest parts of a computer. Because all these devices must communicate with each other over a bus, an efficient transfer mechanism that is not constrained by the slow devices and that can be used to smooth out the differences in timing among processors, memories, and external devices is necessary.
A common approach is to include buffer registers with the devices to hold the information during transfers. To illustrate this technique, consider the transfer of an encoded character from a processor to a character printer. The processor send the character over the bus to the printer buffer. Since the buffer is an electronic register, this transfer requires relatively little time. Once the buffer is loaded, the printer can start printing without further intervention by the processor. The bus and the processor are no longer needed and can be released for other activity. The printer continues printing the character in its buffer and is not available for further transfers until this process is completed. Thus, buffer registers smooth out timing differences among processors, memories and I/O devices. They prevent a high-speed processor from being locked to a slow I/O device during a sequence of data transfers. This allows the processor to switch rapidly from one device to another, interweaving its processing activity with data transfers involving several I/O devices.
Multiple Bus Organization : The three bus structure used to connect the registers and the ALU of a processor. All general-purpose registers are combined into a single block called the register file. In VLSI technology, the most efficient way to implement a number of registers is in the form of an array of memory cells similar to those used in the implementation of random-access memories. The register file is in the figure is said to have three ports. There are two outputs, allowing the contents of two different registers to be accessed simultaneously and have their contents placed on buses A and B. The third port allows the data on bus C to be loaded into a third register during the same clock cycle. Buses A and B are used to transfer the source operands to the A and B inputs of the ALU, where an arithmetic or logic operation may be performed. The result is transferred to the destination over bus C. If needed, the ALU may simply pass one of its two input operands unmodified to bus C. We will call the ALU control signals for such an operation R=A or R=B. The three-bus arrangement obviates the need for registers Y and Z.
A second feature is the introduction of the Incrementer unit, which is used to increment the PC by 4. Using the Incrementer eliminates the need to add 4 to the PC using the main ALU, as was done. The source for the constant 4 at the ALU input multiplexer is still useful. It can be used to increment other addresses, such as the memory addresses in LoadMultiple and Store Multiple instructions.
In step 1, the contents of the PC are passed through the ALU, using the R=B control signal, and loaded into the MAR to start a memory read operation. At the same time the PC is incremented by 4. Note that the value loaded into MAR is the original contents of the PC. The incremented value is loaded into the PC at the end of the clock cycle and with not affect the contents of MAR. In step 2, the processor waits for MFC and loads the data received into MDR, then transfers them to IR in step 3. Finally, the execution phase of the instruction requires only one control step to complete, step-4. By providing more paths for data transfer a significant reduction in the number of clock cycles needed to execute an instruction is achieved.

q1.a

g) Virtual Memory : Virtual memory is a concept which has an ability to address a storage space much larger than primary storage of a particular computer system. Virtual memory is present in the paging sytem. The paging system divides the program into a number of small parts, each part referred as page. And this division is done on logical addresses. So that the programmer does not have to make any decisions about how to divide the program. Paging is entirely transparent to the programmer. The hardware is already ensures that each memory reference and picking up the page base address to use. Using the protection bits. It is already make sure that each page referred to its validity. Each page must be in memory when a program is running. If a process page is not present in memory, an interrupt is generated. The operating system is employed to figure out which page was found to be missing, collect it from disk and changes the page table to indicate the page is now in memory and restarts the program. Swapping allows a number of programs to run at the same time and it is handled entirely by the system-overlays. And it also allows the user to move small parts of program in and out of memory. Virtual memory combines the good features of swapping and overlays. It is like overlays, that only part of the program is in memory at an instance, and the rest of its is not present on disk. The user can sees a large linear virtual address space. Only some parts of the virtual address space are present in physical memory. The rest of its “Virtual” and is reserved on the disk until needed. The disk contains an image of the entire virtual address space, even the parts that are in physical memory. The virtual memory system modules of the operating system maintains the illusion of the virtual memory by moving pages from disk to physical memory when they are needed.
h) Cache Memory : A special very-high speed memory called a cache is sometimes used to increase the speed of processing by making current programs and data available the CPU and a rapid rate. The Cache memory is employed in computer systems to compensate for the speed differential between main memory access time and processor logic. CPU logic is usually faster than main memory access time, with the result the processing speed is limited primarily by the speed of main memory. A technique used to compensate for the mismatch in operating speeds is to employ an extremely fast, a small cache between the CPU and main memory whose access time is close to processor logic clock cycle time. The cache is used for storing segments of programs currently being executed in the CPU and temporary data frequently needed in the present calculations. By making programs and data available at a rapid rate, it is possible to increase the performance rate of the computer. While the I/O processor manages data transfers between auxiliary memory and main memory, the cache organization is concerned with the transfer of information between main memory and CPU. Thus each is involved with a different level in the memory hierarchy system. The reason for having two or three levels of memory hierarchy is economics. As the storage capacity of the memory increases, the cost per bit for storing binary information decreases and the access time of the memory becomes longer. The auxiliary memory has a large storage capacity, is relatively inexpensive, but has low access speed compared to main memory. The cache memory is very small, relatively expensive, and has very high access speed. Thus as the memory access speed increase, so does its relative cost. The overall goal of using a memory hierarchy is to obtain the highest-possible average access speed while minimizing the total cost of the entire memory system. Auxiliary and cache memories are used for different purposes. The cache holds those parts of the program and data that are most heavily used, while the auxiliary memory holds those parts that are not presently used by the CPU. Moreover, the CPU has direct access to both cache and main memory but not to auxiliary memory.
i) Interrupt : Interrupts are used for any infrequent or exceptional event that causes a CPU to temporarily transfer control from its current program to another program. Interrupt handler services the event. Interrupt are the primary mean by which I/O device obtained the services. I/O interrupts are external requests to CPU to initiate or terminate an I/O operation. Interrupts are also produced by hardware or software error detection circuits that invokes error handling routines within the operating system. A power supply failure at any instance, generate an interrupt that request execution of an interrupt handler designed to save critical data about the system’s state. Interrupts generated internally by the CPU are called traps. An operating system will interrupt a user program that exceeds its allotted time. The basic method of interrupting the CPU is by activating a control line with the generic name INTERRUPT REQUEST that connects the interrupt source to CPU. An Interrupt indicator is stored in a CPU register. CPU register is tested periodically, usually at the end of every instruction cycle. On recognizing the presence of interrupt, CPU must execute a specific interrupt servicing program. A problem is caused by the presence of interrupt, CPU must execute a specific interrupt servicing program. A program is caused by the presence of two or more interrupt requests at the same time. Priorities must be assigned to the interrupts and the interrupt with higher priority is selected for service. When interrupt occurs, the following steps are taken by the CPU:
1. CPU identifies the source of the interrupt by polling I/O device.
2. The CPU obtains the memory address of the required interrupt handler
3. This address can be provided by interrupting device along with its interrupt request
4. The program counter(PC) and other CPU status information are saved in memory.
5. The Program counter (PC) is loaded with the address of interrupt handler. Execution proceeds until a return instruction is encountered, which transfer control back to the interrupted program.
j) Half duplex and full duplex transmission :Half duplex transmission system is one that is capable of transmitting in both directions but data can be transmitted in only one direction at a time. A pair of wires is needed for this mode. A common situation is for one modem to act as the transmitter and the other as the receiver. When transmission in one direction is completed, the role of the modems is reversed to enable transmission in the reverse direction. The time required to switch a half-duplex line from one direction to the other is called the turnaround time. A Full duplex transmission can send and receive data in both directions simultaneously. This can be achieved by means of four-wire link, with a different pair of wires dedicated to each direction of transmission. Alternatively , a two-wire circuit can support full-duplex communication if the frequency spectrum is subdivided into two non overlapping frequency bands to create separate receive and transmit channels in the same physical pair of wires.
The communication lines, modems, and other equipment used in the transmission of information between two or more stations is called a data link. The orderly transfer of information in a data link is accomplished by means of a protocol.

q1

Question paper -1
1.Briefly explain the following :-
a) Zero address machine Instruction : A Computer organized using only stack does not use an address field for the arithmetic instructions. However, the PUSH and POP instructions require one address field to specify the operand that moves from/ to the top of stack. Arithmetic expressions re-evaluated by using the top two operands(that is from TOP Stack and one Location below it) and the result is stored on the top of Stack. This implied that the Stack utilized is reduced by one when ever an arithmetic expression is evaluated. The Zero address instructions are so called because of the use of Zero addresses for arithmetic instructions.
Example : x = (A + B) * (C + D)
PUSH A TOS  A
PUSH B TOS B
AND TOS(A+B)
PUSH C TOSC
PUSH D TOSD
ADD TOS(C+D)
MUL TOS(C+D) * (A+B)
POP X TOSM[X] TOS.
b) Microprogramming : A Sequence of micro instructions constitutes a microprogramming. The control unit initiates a series of sequential steps of micro operations during any given time, certain microoperations are to be initiated, while other remain idle. The control variables at any given time can be represented by a string of 1’s and 0’s called a control word. As such, control words can be programmed to perform various operations on the components of the system. A control unit whose binary control variables are stored in memory is called micro programmed control unit. Each word in control memory contains within it a micro instruction. The micro instruction specifies one or more micro operations for the system. A sequence of micro instructions constitutes a micro programming.
c) Bus arbitration: The device that is allowed to initiate data transfers on the bus at any given time is called the bus master. When the current master relinquishes control of the bus, another device can acquire this status. Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. The selection of the bus master must take into account the needs of various devices by establishing a priority system for gaining access to the bus.
There are two approaches to bus arbitration: Centralized and distributed. In Centralized arbitration, a single bus arbiter performs the required arbitration. In distributed arbitration, all devices participate in the selection of the next bus master.
d) Compiler : Compiler is a program which takes one language(source program) as input and translates it into an equivalent another language(target program). During this process of translation if some errors are encountered then compiler display them as error messages. The basic model of computer represented as follows
Input (source program)  compiler  output (Target Program)

e) Hit rate and miss penalty: The performance of cache memory is measured in terms of quality called hit ratio. Cache refers to as an intermediate fast memory space within its memory. It acts as buffer between CPU and Memory. Cache memory provides memory space with greater speed than the memories available. Besides this it provides large memory size with less economical semi-conductor memories. When CPU finds the word in Cache memory is said to produce a “hit”. If the word is not found in cache, and if it is in main memory then it counts as “miss”, the ratio of the number of hits divided by the total CPU references to memory (hit plus misses) is called hit ratio. The average memory-access time of a computer system can be increased by use of a Cache memory. If the hit ratio is high then CPU access cache instead of main memory. The average access time is closer to the access time of the fast cache memory.

assembly language

List and Explain Assembler directives
The following directives are commonly used in the assembly language programming practice using Micro Soft Micro Assembler or Turbo Assembler.
DB: Define Byte The DB directive is used to reserve byte or bytes of memory location in the available memory. While preparing the EXE file, this directive directs the assembler to allocate the specified number of memory bytes to the said data type that many be a constant, variable, string etc.,
The following examples show how the DB directive is used for different purposes.
Example:
RANKS DB 01H, 02H, 03H, 04H.
This statement directs the assembler to reserve four memory locations for a list named RANKS and initialize them with the above specified values.
MESSAGE DB ‘good morning’
This makes the assembler reserves number of bytes of memory equal to the number of characters in the string named MESSAGE and initialize those locations by the ASCII equivalent of these characters
VALUE DB 50H
This statement directs the assembler to reserve 50H memory bytes and leave them uninitialized for the variable named VALUE.
DW: Define word
The DW directive directs the same purpose as the DB directive, but it now make the assembler reserve the number of memory words(16 bit) instead of bytes.
Example :
WORDS DW 1234H, 4567H, 78ABH, 645CH
The DW makes the assembler reserve four words in memory(8 bytes), and initialize the words with the specified values in the statements. The lower bytes are stored in the lower memory addresses, while the upper bytes and stored at the higher addresses, during initialization. Another option of the DW directive is explained with the DUP operator.
WDATA DW 5 DUP (6666H)
This statement reserves five words, that is 10-bytes of memory for a word label WDATA and initializes all word locations with 6666H.
DQ: Define Quadword : DQ directive is used to direct the assembler to reserve 4 words (8 bytes) of memory for the specified values.
DT: Define ten bytes : The DT directive directs the assembler to define the specified variable requiring 10-bytes for its storage and initialize the 10-bytes with the specified values.
ASSUME: Assume logical segment Name : Assume directive is used to inform the assembler, the names of the logical segment to be assumed for different segments which is used in the program. In the assembly language program, each segment is given a name. For example, the code segment may be given the name DATA etc. The statement ASSUME CS: CODE directs the assembler that the machine code are available in a segment named CODE, and thus the CS register is to be loaded with the address(segment) allotted by the operating system for the label CODE, while loading. The ASSUME statement is must to start each assembly language program, without a message. ‘CODE/DATA EMITTED WITHOUT SEGMENT’ may be issued by an assembler.
END: End of program : The END directive marks the end of an assembly language program. When the assembler comes across END directive, it ignores the source lines available later on.
ENDP: END of procedure: The subroutines are called procedures in assembly language programming. They may be independent program modules which return the particular result or values to the calling programs. The ENDP directive is used to end of a procedure. A procedure is usually assigned as a name that is label.
To mark the end of a particular procedure, the name of the procedure, that is label may appear as a prefix with the directive ENDP. The statements appearing in the same module but after the ENDP directive are neglected from that procedure. The following illustration explains the use of ENDP.
PROCEDURE STAR
.
.
.
STAR ENDP
ENDS: End of Segment
The ENDS directive marks the end of a logical segment. The logical segments are assigned with the names using the ASSUME directive. The names appear with the ENDS directive as prefixes to mark the end of those particular segments. Whatever are the contents of the segment they should appear in the program before ENDS. Any statement appearing after ENDS will be neglected from the segment. The following structure explains the above mention detail more clearly.
DATA SEGMENT
..
..
DATA ENDS
ASSUME CS: CODE, DS: DATA
..
..
CODE ENDS
END
EVEN: Align on Even Memory Address
The assembler, while starting the assembling procedure of any program, initializes a location counter and goes on updating it, as the assembly proceeds. It goes on assigning the available addresses, that is the contents of the location counter, sequentially to the program variables, constants and modules as per their requirements, in the sequence in which they appear in the program. The EVEN directive updates the next even address of the current location, counter contents are not even, and assign the following routine or variable or constant to that address. The following structure explains the directive.
EVEN
PROCEDURE ROOT
..
..
ROOT ENDP
EQU : Equate
The EQU directive is used to assign a label with a value or a symbol. It is used to reduce the recurrence of the numerical values or constants in a program code. Using the EQU directive, even an instruction mnemonics can be assigned with a label, which can be used in the program in place of that mnemonic.
The following example shows the syntax.
Example :
LABEL EQU 0500H
ADDITION EQU ADD
The first statement assign the constant 500H with the label LABEL, while in the second statement assigns another label ADDITION with mnemonic ADD.
EXTRN : External and PUBLIC : Public
The EXTRN directive informs the assembler that the names, procedures and labels declared after this directive have already been defined in some other assembly language modules. While in the other module, where the names, procedures and lables appear they must be declared as public, using the PUBLIC directive.
MODULE1 SEGMENT
PUBLIC FACTORIAL FAR
MODULE1 ENDS
MODULE2 SEGMENT
EXTRN FACTORIAL FAR
MODULE2 ENDS.

GROUP: Group the Related Segments
The GROUP directive is used to form logical groups of segments with similar purpose or type. It is used to inform the assembler to form a logical group of the following segment names. Thus all such segments and labels can be addressed using the same segment base.
Program group code, data, stack
The above statement directs the loader/linker to prepare an EXE file such that CODE, DATA and STACK segment must be within a 64k byte memory segment that is named as PROGRAM. Now, for ASSUME statement, one can use the label PROGRAM rather than CODE, DATA and STACK as shown
ASSUME CS: PROGRAM, DS; PROGRAM, SS: PROGRAM.
LABEL: Label
The LABEL directive is used to assign a name to the current content of the location counter. When the assembly process starts the assembler initializes a location counter to keep track of memory locations assigned to the program. As the program assembly proceeds, the contents of the location counter are updated. During the assembly process, whenever the assembler comes across the LABEL directive, it assigns the declared label with the current contents of the location counter.
LENGTH: Byte length of a label
This directive is not available in MASM, and used to refer the length of a data array or a string.
MOV CX, LENGTH ARRAY
This statement, when assembled, will substitute the length of the array ARRAY in bytes, in the instruction.
LOCAL
The labels, variables, constants or procedures declared LOCAL in a module are to be used only by that particular module.
Example:
LOCAL a,b DATA, ARRAY, ROUTINE.
NAME: Local NAME of a Module
The NAME directive is used to assign a name to an assembly language program module. The module, may now be referred by its declared name.
OFFSET: Offset of a Label
When the assembler comes across the OFFSET operator along with a Label, it first computes the 16-b it displacement(also called as offset interchangeably) of the particular label, and replaces the string ‘OFFSET LABEL’ by the computed displacement. This operator is used with arrays, strings, labels and procedures to decide their offsets in their default segments.
The examples of OFFSET operator are as follows:
Example :
CODE SEGMENT
MOVE SI, OFFSET LIST
CODE ENDS
DATA SEGMENT
LIST DB 10 H
DATA ENDS
ORG: Origin
The ORG directive directs the assembler to start the memory allotment for the particular segment, block or code from the declared address in the ORG statement. The location counter is initialized to 0000 if the ORG statement is not written in the program. If an ORG 200H statement is present at the starting of the code segment of the module, then the code will start from 200H address in code segment.
PROC: Procedure
The PROC directive marks the start of a named procedure in the statement. And also the types NEAR or FAR specify the type of the procedure. That is, whether it is to be called by the main program located within 64k of physical memory or not.
Example :
RESULT PROC NEAR
ROUTINE PROC FAR
PTR: Pointer
The POINTER Operator is used to declare the types of label, variable or memory operand. The operator PTR is prefixed by either BYTE or WORD.
PUBLIC:
The PUBLIC directive is used along with the EXTRN directive. And informs the assembler that the labels, variables, constants or procedures declared PUBLIC may be accessed by other modules. But while using the EXTRN declared labels, variables, constants or procedures, the user must declare them external using the EXTRN directive.
SEG: Segment of a Label
The SEG operator is used to decide the segment address of the label, variable, or procedure and substitutes the segment base address in place of “SEG” label.
Example:
MOV AX, SEG ARRAY ; This statement moves the segment address of ARRAY in
MOV DS,AX ; Which it is appearing, to register AX and then to DS.
SEGMENT: Logical Segment
The SEGMENT directive marks the starting of a logical segment. The started segment is also assigned a name that is label, by the statement. In some cases, the segment may be assigned a type like PUBLIC or GLOBAL (can be accessed by any other modules)
Examples:
EXE CODE SEGMENT GLOBAL
; start of segment named EXE.CODE
; that can be accessed by any other module
EXE. CODE ENDS; END of EXE.CODE logical segment
SHORT
The SHORT operator indicates to the assembler that only one byte is required to code the displacement for a jump(that is displacement is within -128 to +127 bytes from the address of the byte next to the jump.
Example:
JMP SHORT LABEL
TYPE:
The TYPE operator directs the assembler to decide data type of the specified label and replaces the ‘TYPE’ label by the decided data type. For the word type variable, the data type is 2, for the double word type, it is 4, and for byte type 1.
GLOBAL
The labels, variables, constants or procedures declared GLOBAL may be used by other modules of the program.
Example:
ROUTINE PROC GLOBAL
‘+’ & ‘-‘ Operators:
These operators represent arithmetic addition and subtraction respectively and they are typically used to add or substract displacements(8 or 16 bit) to base, index etc.
Example:
MOV AL, [SI + 2]
MOV DX, [BX -5]
MOV BX, [OFFSET LABEL F10H]
MOV AX, [B + 91]
FARPTR:
The FAR PTR directive indicates the assembler that label following FAR PTR is not available within the segment and the address of the label is 32 bits, that is 2 bytes offset followed by 2 bytes segment address
Example:
JMP FAR PTR LABEL
CALL FAR PTR ROUTINE
NEAR PTR
The NEAR PTR directive indicates the label following NEAR PTR is in the same segment and requires only 16-bit that is 2 byte offset to address it.
Example:
JMP NEAR PTR LABEL
CALL NEAR PTR ROUTINE

computer arithmetic

COMPUTER ARITHMETIC
A basic operation in all digital computers is the addition or subtraction of two numbers. Arithmetic operations occur at the machine instruction level. They are implemented, along with basic logic functions such as AND,OR, NOT, and exclusive –OR (XOR), in the arithmetic logic unit(ALU) subsystem of the processor. We use logic Circuits to implement arithmetic operations, The time needed to perform and addition operation affects the processor’s performance. Multiply and divide operations, which require more complex circuitry than either addition or subtraction operations, also affect performance. We present some of the techniques used in modern computers to perform arithmetic operations at high speed.
Compared with arithmetic operations, logic operations are simple to implement using combinational circuitry. They require only independent Boolean operations on individual bit positions of the operands, whereas carry/borrow lateral signals are required in arithmetic operations.
ADDITION AND SUBTRACTION OF SIGNED NUMBERS
There will arise instances when we need to express numbers that are less than zero. These numbers are called signed numbers and consist of positive(+) and
negative(-) numbers. Positive numbers are greater than zero and negative numbers are less than zero.
Positive and negative whole numbers are called integers while signed fractions and decimals are called rational numbers. It is not necessary to write the + for a positive number unless you want to draw attention to the fact that it is positive. The negative sign must always in used for a negative number.
A number line for integers continues indefinitely in both the negative and positive directions. Numbers get smaller as we proceed to the left and larger to the right. The opposite of a number is the number the same distance from zero but in the opposite direction.

In order to perform operations with signed numbers, we need to define the absolute value of a number. The absolute value of a number, symbolized by placing the number between 2 vertical bars (l l) is defined to be the distance that number is located from zero on a number line without regard to the direction.
• |3| = 3
• |-5| = 5

When you add two numbers with the same signs add the absolute values, and write the sum (the answer) with the sign of the numbers. If the sign is positive, it is commonly omitted.
5 + 16 = 21
-12 + -15 = -27
Binary Addition Basic Rules for Binary Addition
0+0 = 0 0 plus 0 equals 0
0+1 = 1 0 plus 1 equals 1
1+0 = 1 1 plus 0 equals 1
1+1 = 10 1 plus 1 equals 0
with a carry of 1 (binary 2)
The technique of addition for binary numbers is similar to that for decimal numbers, except that a 1 is carried to the next column after two 1s are added.
Example: Add the numbers 310 and 110 in binary form.
Solution
The numbers, in binary form, are 11 and 01.
11
01
100
In the right-hand column, 1 + 1 = 0 with a carry of 1 to the next column.
In the next column, 1+0+1 = 0 with a carry of 1 to the next column.
In the left-hand column, 1 + 0 + 0 = 1. Thus, in binary, 11 + 01 = 100 = 410.
Binary Subtraction Basic Rules for Binary Subtraction
0 − 0 = 0 0 minus 0 equals 0
1 − 1 = 0 1 minus 1 equals 0
1 − 0 = 1 1 minus 0 equals 1
10 − 1 = 1 10 minus 1 equals 1

Example: Subtract 310 = 11 from 510 = 101 in binary form.
Solution
The subtraction procedure is shown below.
1 0 1
− 0 1 1
0


1 0 1
− 0 1 1
0


1 0 1
− 0 1 1
1 0

1 0 1
− 0 1 1
0 1 0

Starting from the left, the first array is the subtraction in the right hand column. In the second array, a 1 is borrowed from the third column for the middle column at the top and paid back at the bottom of the third column. The third array is the subtraction 10 − 1 = 1 in the middle column. The final array is the subtraction 1 − 1 = 0 and the final answer is thus 10 = 210.

Interrupts

5Q. What is interrupt ? Explain Priority interrupt and Daisy chain interrupt and parallel priority interrupt system with necessary diagram?
Ans : The program enters a wait loop in which it repeatedly tests the device status. During this period, the processor is not performing any useful computation. There are many situations where other tasks can be performed while waiting for an I/O device to become ready. To allow this to happen, we can arrange for the I/O device to alert the processor when it becomes ready. It can do so by sending a hardware signal called an interrupt to the processor.

Priority Interrupt: A priority interrupt is a system that establishes a priority over the various sources to determine the condition which is to be serviced first, when two or more requests arrive simultaneously.
The system may also determine which conditions are permitted to interrupt the computer while another interrupt is being serviced. Higher priority interrupt levels are assigned to requests which, if delay or interrupted, could have serious consequences. When two devices interrupt the computer at the same time, the computer services the device, with the higher priority first.
Establishing the priority of simultaneous interrupts can be done by software or hardware. A polling procedure is used to identify the highest priority source by software means. In this method there is one common branch addresses for all interrupts the Program that takes care of interrupts begins of the branch address and polls the interrupt sources in sequence. The order in which they are tested determines the priority of each interrupt.
The initial service routine for all interrupts consists of a program that tests the interrupt sources in sequence and branches to one of many possible services routines. The particular service routine reached belongs to the highest-priority device among all devices interrupted the computer. The drawback of the software method is that, the time required to poll them can exceed the time available to service the I/O device, if there are many interrupts. In this situation a hardware priority-interrupt can be used to speed up the operation.
A hardware priority-interrupt unit functions as an overall manager in an interrupt system environment. Each interrupt source has its own interrupt vector to access its own service routine directly, to speed up the operation. The hardware priority function can be established by either a serial or a parallel connection of interrupt lines. The serial connection is also known as the daisy-chaining method.
Daisy-chaining Priority : The daisy-chaining method of establishing priority consists of a serial connection of all devices that request an interrupt. The device with the highest priority is placed in the first position, followed by lower-priority devices upto the device with the lowest priority, which is placed last in the chain. The following figure demonstrate the method of connection between three devices and the CPU.









The interrupt request line is common to all devices and forms a wired logic connection. If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU. The interrupt line stays in the high-level state and no interrupts are recognized by the CPU, only when no interrupts are pending. And is equivalent to a negative logic or operation. The CPU responds to an interrupt request by enabling the interrupt acknowledge line.
This signal is received by device 1 at its PI(priority in) input. The acknowledge signal passes on the next device through the PO(Priority Out) Output only if device 1 is not requesting an interrupt. It blocks the acknowledgement signal from the next device by placing a 0 in the PO output, if device I has a pending interrupt. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the CPU to use, during the interrupt cycle.
A device with a 0 in its PI input generate a O in its PO output to inform the next-lower-priority device that the acknowledge signal has been blocked. A device that is requesting an interrupt and has a 1 in its PI input will intercept the acknowledge signal by placing a O in its PO output. It transmits the acknowledge signal to the next device by placing in 1 in its PC Output, if the device does not have pending interrupts.
Thus the device with PI = 1 and PO = 0 is the one with the highest priority that is requesting an interrupt, and this device places its vector address (VAD) on the data bus. The daisy chain arrangement gives the highest priority to the device that receives the interrupt acknowledge signal from the CPU. The farther the device is from the first position; the lower is its priority.
Parallel Priority Interrupt: The parallel priority interrupt method uses a register whose bits are set separately by the interrupt signal from each device. Priority is established according to the position of the bits in the register. The circuit may include a mask register whose purpose is to control the status of each interrupt request in addition to the interrupt register. The mask register can be programmed to disable lower-priority interrupts while a higher priority device is being serviced. It also provides a facility that allows a high priority device to interrupt the CPU while a lower-priority device is being serviced.
The Priority logic for a system of four interrupt sources is demonstrated in the previous figure. It consists of an interrupt register whose individual bits are set by external conditions and cleared by program instructions. The magnetic disk being a high-speed device, is given the highest priority. The printer has the next priority followed by a character reader and a keyboard. The mask register has the same number of bits as the interrupt register.
By means of program instructions, it is possible to set or reset any bit in the mask register. Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four inputs to a priority encoder. In this way an interrupt is recognized only if its corresponding mask bit is set to 1 by the program. The priority encoder generates two bits of the vector address, which is transferred to the CPU.
Another output from the encoder sets an interrupt status flip-flop IST when an interrupt that is not masked occurs. The interrupt enable flip-flop IEN can be set or cleared by the program to provide an overall control over the interrupt system. The output of IST ANDed with IEN provide a common interrupt signal for the CPU. The interrupt acknowledge INTACK signal from the CPU enables the bus buffers in the output register and a vector address VAD is placed into the data bus

Assign-3

1Q : Explain about Synchronous Bus and Asynchronous Bus?
2Q : Explain about Standard I/O Interfaces ?
3Q : Explain about PCI Bus ?
4Q : Explain about SCSI Bus?
5Q : Explain about Universal Serial Bus ?
6Q : Differenciate Parallel and Serial I/O Interfaces?
7Q : Discuss I/O Versus Memory Bus?
8Q : Explain in detail about different modes of transfers?
9Q : What is priority interrupt ? Explain Daisy chain interrupt and
parallel priotity interrupt system with necessary diagrams
10Q : Explain indetail about Addition and Subtraction of Signed Numbers ?

I/O

1. What is input –output interface? Discuss different types of interfaces?
Input-Output Interface: Input-Output Interface provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. The purpose of the communication link is to resolve the differences that exist between the central computer and each peripheral. Data transfer rate of systems include special hardware components between the CPU and peripherals to supervise and synchronize all input transfers. These components are called interface units because they interface between the processor bus and the peripheral device.
There are basically 2 types of interfaces. 1) Parallel Interface 2) Serial Interface
In Parallel interface, there are multiple lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously that is all the bits of a word are transferred simultaneously over the data bus. In serial interface there is only one line used to transmit data and bits are transmitted one at a time. A parallel Interface is commonly used for higher-speed peripherals. Like tape and disk where as serial is used for printer and terminals
In addition, each device may have its own controller that supervises the operations of the particular mechanism in the peripheral.
I/O Bus and Interface Modules: A typical communication link between the processor and several peripherals is designed in order to attain a full fledged communication between them. The I/O bus consists data lines, address lines and control lines. The magnetic disk, printer, and terminal are employed in particularly any general purpose computer. The magnetic tape is used in some computers for backup storage. Each peripherals device has associated with it an interface unit. A controller may be housed separately or may be physically integrated with the peripheral. The I/O bus from the processor is attached to all peripheral interfaces.
To communicate with a particular device, the processor places a device address on the address lines. A interface unit is associated with each peripheral device and its function is to decode the address lines and find out whether the address belongs to that device. Once the interface decodes the signal on the address lines and identifies that the address belongs to the peripheral associated with the interface, the peripheral device is switched on. Each peripheral has controller associated with the device. Like, if the output device is a printer, the printer controller controls the movement of paper, aligning in the proper place and selecting the printing characters to be printed. A peripheral controller is either integrated with the device or housed as part of the device. Once the control is set properly, data may be transferred from the CPU to peripheral device or vice versa through data lines. Below figure shows the Interfacing CPU to Peripheral devices.
2Q : Discuss I/O versus Memory Bus
I/O Versus Memory Bus: Processor should communicate with both I/O and memory unit like the I/O bus, the memory bus contain data, address, and read/write control lines. There are three ways that computer buses can be used to communicate with memory and I/O.
1. Use two separate buses, one for memory and the other for I/O
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control lines.
In first method, the computer has independent sets of data, address and control buses, one for accessing memory and the other for I/O. And it is done in computers which provide a separate I/O processor (I/O processor) in addition to the central processing unit (CPU). The memory communicates with both the CPU and the I/O processor through a memory bus. The I/O processor communicates with both the CPU and I/O processor through a memory bus. The I/O processor also communicates with the input and output devices through a separate I/O bus with its own address, data and control lines. The purpose of the I/O processor is to provide an independent pathway for the transfer of information between external devices and internal memory. The I/O processor is sometime also known as data channel.

3Q. Differentiate between memory mapped and isolated I/O
Ans : Many computers use on common bus to transfer information between memory or I/O and the CPU. The distinction between a memory transfer and I/O transfer is made through separate read and write lines. The CPU specifies whether the address on the address lines is for a memory word of for an interface register by enabling one of two possible read or write lines. This configuration isolates all I/O interface address from the address assigned to memory and is referred to as the isolated I/O method for assigning address in a common bus.
Isolated I/O : Isolated I/O is a configuration maintaining independent set of input and output instructions. The central processing unit receives the opcode of a given instruction, decodes it and transmits the address of the given peripheral device on the common address lines shared by processor, memory and other I/O peripherals. Therefore, CPU performs the derived operation that is either I/O read or I/O write control lines.
Memory mapped I/O : The CPU maintains common address space for both units that is memory as well as I/O Unit. Therefore, the CPU utilizes the registers such as data and status registers which belongs to I/O Units as a memory space for storing various addresses.

4Q. Explain in detail about different modes of transfers:
Ans : Modes of Transfer : The CPU merely executes the I/O instructions and may accept the data temporarily, but the ultimate source or destination is the memory unit. Data transfer between the central computer and I/O devices may be handled in a variety of modes. Data transfer to and from peripherals may be handled in one of the three possible modes:
1) Programmed I/O
2) Interrupt Driven I/O
3) Direct memory access (DMA)
Programmed I/O : In Programmed I/O approach, the transfer of data item is initiated by an instruction in the computer program. The data transfer in between a CPU register and ( a register in the ) peripheral and is useful in low speed computer systems to minimize hardware costs. The data is transferred between a register in CPU and another (buffer) register in the peripheral. For example, IN and OUT instructions in 8085 processor for performing data transfer between accumulator and a register in the peripheral devices. Some more instructions may be required to transfer the data into memory from accumulator on the CPU side and between the buffer ends into the appropriate location in the peripheral device.
A constant monitoring of the peripheral by CPU is required to transfer data under program control. The CPU is required to monitor the interface of the peripheral device to find out when and additional data transfer takes place. The instructions executed in CPU monitor the various registers to ensure that data transfer takes place smoothly without any overriding of data items or loss of data items. The CPU must stay in the program loop until the I/O interfacing unit informs that it is ready for data transfer to take place. And this mechanism keeps the processor busy for a very long time.
Interrupt-Driven I/O : Interrupt Driven I/O approach of data transfer reduces the requirements on processor time as compared to the programmed approach to input and output data transfer. An interrupt is used to indicate to the CPU that it is ready to accept data for transfer from CPU or a data item is available for transfer, CPU executes another program and therefore the demand on CPU time is reduced. During the period CPU is executing other programs, I/O interface monitors continually the external device and generates an interrupt signal (request) to the computer. CPU suspends the present task and branches to an interrupt service routine. When an interrupt signal is detected.
The interrupt service routine, which indicates the action required, is executed and at the end of the execution of interrupt service routine, CPU returns to the program that it was originally executing. The interruption of CPU Program is planned at the beginning of fetching any instruction, the system checks from any interrupt Driven I/O and programmed I/O are useful when the amount of data required to be transferred is small. Only one byte or word can be transferred each time. If large volumes of data are required to be transferred another approach is used.
Direct Memory Access: (DMA)
The Direct Memory Access is used for the transferring large volumes of data between main memory and a peripheral device through the memory bus. In the DMA approach the CPU initiates the data transfer by supplying the interface, the starting address of the data and the number of words of data the execution of other instructions. During DMA period, CPU will not be able to access memory to execute other instructions. The CPU allows the memory use to be controlled by IO data transfer during DMA operations. At the end of DMA operations. The CPU has to delay all memory access operations during direct memory – I/O transfer are much less frequent than processor to memory access operations.
Many computer systems use an I/O processor which combined the interface logic with direct memory access operations. A large number of peripheral devices can be handled by an I/O processor with the help of interrupts and DMA facility. Such computer system can be treated as serving three separate modules. A memory unit, CPU and an I/O Processor.

Evolution

CS224 COMPUTER ARCHITECURE AND ORGANIZATION
Review of Computer Systems :
The Evolution of Computers
Development of the technologies used to fabricate the processors, memories and I/O units of computers has been divided into four generations:
1st Generation (1945-1955) :
o Vacuum tubes were used to perform logic operations and to store data.
o The key concept of a stored program was introduced by John Von Neumann.
o Programs and their data were located in the same memory, as they are today
o Assembly language was used to prepare programs and was translated into machine language for execution
o Basic arithmetic operations were performed in a few milliseconds using vacuum tube technology to implement logic functions.
o This provided 100- to 1000- fold increase in speed relative to the earlier mechanical and relay based electro mechanical technology.
o Mercury delay – line memory was used at first, and I/O functions were performed by devices similar to type writers.
o Magnetic core memories and magnetic tape storage devices were also developed.
2nd Generation (1955-1965):
o Transistor was invented at AT&T Bell Laboratories
o Magnetic core memories and magnetic drum storage devices were used
o High level languages, such as Fortran was developed, making the preparation of application programs much easier
o System programs called compilers were developed to translate these high-level language programs into the corresponding assembly language program, which was then translated into the executable machine language form.
o Separate I/O processors were developed that could operate in parallel with the central processor that executed programs, thus improved overall performance.
3rd Generation (1965-1975):
o IC (Integrated Circuit) Technology was introduced where the many transistors were fabricated on a single silicon chip
o IC memories replaced magnetic core memories
o Other developments included the introduction of microprogramming, parallelism, and pipelining.
o Operating system software allowed efficient sharing of computer system by several user programs.
o Cache and Virtual memories were developed
o Cache memory makes the main memory appear faster than it really is
o Virtual memory makes it appear larger
o System 360 mainframe computers from IBM and the line of PDP minicomputers from Digital Equipment Corporation were dominant commercial products of the third generation.
4th Generation (1975 to Present):
o Very Large Scale Integrated (VLSI) Technology allowed a complete processor to be fabricated on a single chip is microprocessor. Intel Company played major role.
o Organizational concepts such as concurrency, pipelining, caches and virtual memories evolved to produce the high-performance computing systems
o Portable notebook computers, desktop personal computers and workstations, interconnected by LAN, WAN and Internet have become dominant mode of computing.

Touch Pad

A touch pad (also called track pad) is a pointing device consisting of specialized surface that can translate the motion and position of a user’s fingers to a relative position on screen. They are a common feature of laptop computers and also used as a substitute for a computer mouse where desk space is limited. Touch pads vary in size but are rarely made larger than 40 square centimeters (6.3 X 6.3 cm or about 6 inch²). They can also be found on personal digital assistants (PDAs) and some portable media players, such as the ipod using the click wheel. A touchpad is perhaps the most common kind of tactile sensor.

MEMORY HIERARCHY

MEMORY ORGANIZATION AND MEMORY HEIRARCHY

MAIN MEMORY

The main memory is the central storage unit in a computer system. It is a relatively large and fast memory used to store programs and data during the computer operation. The principal technology used for the main memory is based on semiconductor integrated circuits. Integrated circuit RAM chips are available in two possible operating modes, static and dynamic.

The static RAM consists essentially of internal flip-flops that store the binary information. The stored information remains valid as long as power is applied to the unit.

The dynamic RAM stores the binary information in the form of electric charges that are applied to capacitors. The capacitors are provided inside the chip by MOS transistors. The stored charge on the capacitors tend to discharge with time and the capacitors must be periodically recharged by refreshing the dynamic memory. Refreshing is done by cycling through the words every few milliseconds to store the delying charge. The dynamic RAM offers reduced power consumption and larger storage capacity in a single memory chip.

The static RAM is easier to use and has shorter read and write cycles.

Most of the main memory in a general –purpose computer is made up of RAM integrated circuit chips, but a portion of the memory may be constructed with ROM chips. Originally, RAM was used to refer to a random-access memory, but now it is used to designate a read/write memory to distinguish it from a read-only memory, although ROM is also random access. RAM is used for storing the bulk of the programs and data that are subject to change. ROM is used for storing programs that are permanently resident in the computer and for tables of constants that do not change in value once the production of the computer is completed.

The ROM portion of main memory is needed for storing an initial program called a bootstrap loader. The bootstrap loader is a program whose function is to start the computer software operating when power is turned on. Since RAM is volatile, its contents are destroyed when power is turned off. The contents of ROM remain unchanged after power is turned off and on again. The startup of a computer consists of turning the power on and starting the execution of an initial program. Thus, when power is turned on, the hardware of the computer sets the program counter to the first address of the bootstrap loader. The bootstrap program loads a portion of the operating system from disk to main memory and control is then transferred to the operating system, which prepares the computer for general use.

RAM and ROM chips are available in a variety of sizes. If the memory needed for the computer is larger than the capacity of one chip, it is necessary to combine a number of chips to form the required memory size.

AUXILIARY MEMORY

The Auxiliary memory devices used in a computer system are magnetic disk, tapes, magnetic drums and more recently optical disks. The important features of any devices are its access mode, access time, transfer rate, capacity and cost.

The average time to reach a storage location in memory and obtain its contents is the access time. In electro-mechanical devices access time is equal to the sum of seek time (time required to position the read, write heads and on the location) and transfer time(the time required to transfer data to and from any device). Auxiliary storage is logically divided into records or blocks. A record/block consists of a number of words. Input/Output from /on auxiliary memory is always done to enter blocks.

ASSOCIATIVE MEMORY

Many data processing applications require that the time required to find an item stored in memory be reduced to a minimum for efficiency. This can be done if stored data can be identified for access by content of the data rather than by its address. A memory unit addressed by its contents is called associative memory or content addressable memory (CAM). This type of memory can be accessed simultaneously in parallel on basis of data content. When a word is to be written into associative memory no address is specified, it is capable of finding an empty unused location to store the word. When a word is read from the memory, the content or part of the word is specified, the memory hardware locates all words which match the content and mark them for reading.

CACHE MEMORY

Analysis of a large number of typical programs has shown that the reference to memory at any given interval of time tend to be confined within a few localized areas in memory. This phenonmenon is known as the property of locality of reference. The reason for this property may be understood considering that a typical computer program flows in a straight line fashion with program loops and subroutine calls encountered frequently?

When a program loop is executed, the CPU repeatedly refers to the set of instructions in memory that constitute the loop. Every time a given subroutine is called, its set of instructions are fetched from memory. Thus, loops and subroutines tend to localize the references to memory for fetching instructions. To a lesser degree, memory references to data also send to be localized. Table-loopup procedures repeatedly refer to that portion in memory where the table is stored. Iterative procedures refer to common memory locations and array of numbers are confined within a local portion of memory. The result of all these observations is the locality of reference property, which states that over a short interval of time, the addresses generated by a typical program refer to a few localized areas of memory repeatedly, while the remainder of memory is accessed relatively infrequently.

If the active portions of the program and data are placed in a fast small memory, the average memory access time can be reduced, thus reducing the total execution time of the program. Such a fast small memory is referred to as a cache memory. It is placed between the CPU and main memory as shown in the figure. The cache is the fastest component in the memory hierarchy and approaches the speed of CPU components.

The fundamental idea of cache organization is that by keeping the most frequency accessed instructions and data in the fast cache memory, the average age memory access time will approach the access time of the cache. Although the cache is only a small fraction of the size of main memory, a large fraction of memory requests will be found in the fast cache memory because of the locality of reference property of programs.

The basic operation of the cache is as follows. When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is read from the fast memory. If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the word. A block of words containing the one just accessed is then transferred from main memory to cache memory. The block size may vary from one word(in one just accessed) to about 16 words adjacent to the one just accessed. In this manner, some data are transferred to the cache so that future references to memory find the required words in the fast cache memory

The performance of cache memory is frequently measured in terms of a quantity called hit ratio. When the CPU refers to memory and finds the word in cache, it is said to produce a hit. If the word is not found in cache, it is in main memory and it counts as a miss. The ratio of the number of hits divided by the total CPU references to memory(hits plus misses) is the hit ratio. The hit ratio is best measured experimentally by running representative programs in the computer and measuring the number of hits and misses during a given interval of time. Hit ratios of 0.9 and higher have been reported. This high ratio verified the validity of the locality of reference property.

The average memory access time of a computer system can be improved considerably by use of a cache. If the hit ratio is high enough so that most of the time the CPU accesses the cache instead of main memory, the average access time is closer to the access time of the fast cache memory. For example, a computer with cache access time of 100 ns, a main memory access time of 1000 ns, and a hit ratio of 0.9 produces an average access time of 200 ns. This is a considerable improvement over a similar computer without a cache memory, whose access time is 1000 ns.

The basic characteristic of cache memory is its fast access time. Therefore, very little or no time must be wasted when searching for words in the cache. The transformation of data from main memory to cache memory is referred to as a mapping process. Three types of mapping procedures are of practical interest when considering the organization of cache memory:

1.      Associative mapping

2.      Direct mapping

3.      Set-associative mapping

Memory

Memory Unit : A memory unit is a collection of storage cells together with associated circuits needed to transfer information in and out of storage. The memory stores binary information in groups of bits called words. A word in memory is an entity of bits that move in and out of storage as a unit. A memory word is a group of 1’s and 0’s and may represent a number, an instruction code, one or more alphanumeric characters, or any other binary-coded information. There are two types of memories are used in computer systems: 1) Random-Access-Memory(RAM) 2) Read-Only-Memory
Types of ROM : The required path in a ROM may be programmed in three different ways. The first, mask programming, is done by the semiconductor company during the last fabrication process of the unit. The procedure for fabricating a ROM requires that the customer fill out the truth table that he or she wishes the ROM to satisfy. The truth table may be submitted in a special form provided by the manufacturer or in a specified format on a computer output medium. The manufacturer makes the corresponding mask for the paths to produce the 1’s and 0’s according to the customer’s truth table. This procedure is costly because the vendor charges the customer a special fee for custom masking the particular ROM. For this reasons mask programming is economical only if a large quantity of the same ROM configuration is to be ordered.
For small quantities it is more economical to use a second type of ROM called a programmable –read only memory or PROM. When ordered, PROM units contain all the fuses intact, giving all 1’s in the bits of the stored words. The fuses in the PROM are blown by application of current pulses through the output terminals for each address. A blown fuse defines a binary 0 state, and an intact fuse gives a binary 1 state. This allows user to program PROMs in their own laboratories to achieve the desired relationship between the input addresses and stored words. Special instruments called PROM programmers are available commercially to facilitate this procedure. In any case, all procedures for programming ROMs are hardware procedures even though the word “programming” is used.
The hardware procedure for programming ROMs or PROMs is irreversible, and once programmed, the fixed pattern is permanent and cannot be altered. Once a bit pattern has been established, the unit must be discarded if the bit pattern is to be changed. A third type of ROM available is called erasable PROM or EPROM.
The EPROM can be restructured to the initial value even though its fuses have been blown previously. When the EPROM is placed under a special ultraviolet light for a given period of time, the shortwave radiation discharges the internal gates that serve as fuses. After erasure, the EPROM returns to its initial state and can be reprogrammed to a new set of words. Certain PROMs can be erased with electrical signals instead of ultraviolet light. These PROMs are called electrically erasable PROM or EEPROM. Flash memory is a form of EEPROM in which a block of bytes can be erased in a very short duration. Example applications of EEPROM devices are :
1. Storing current time and date in a machine.
2. Storing port statuses
Examples of flash memory device applications are:
1. storing messages in a mobile phone.
2.storing photographs in a digital camera.

Assignment

Assignment -I
1. Explain Computer Organization, Computer Design and Computer Architecture
2. Explain the Evoluation of Computer
3. Explain the Functional Units of Digital Computer With the help of a block diagram
4. Explain the difference between Magnetic Tapes and Magnetic Disks
5. Explain the Instruction Execution steps involved in CPU?
6. Explain the Basic Operational Concepts and Connections between the processor and  the main memory?
7. What do you mean by Logic Gates and Explain with the help of Truth Table?
8. Explain about r's complement and r-1 complement with proper examples.

RISC&CISC

RISC : It means Reduced Instruction Set Computer, it is a computer with fewer instructions with simple constructs, so they can be executed much faster within the CPU without having to use memory as often. This type of computer is classified as a reduced instruction set computer or RISC.
RISC characteristics
1. Relatively few instructions
2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations done within the registers of the CPU
5. Fixed length, easily decoded instruction format
6. Single cycle instruction execution, relatively large no of registers in the processor unit
7. Hardware rather than micro programmed control
8. RISC systems shorten execution time by reducing the clock cycles per instruction ( that is simple instructions take less time to interrupt)

CISC : It means complex instruction set computer, A computer with large number of instructions is classified as a complex instruction set computer.
Characteristics of CISC
1. A large number of instructions typically from 100 to 250 instructions
2. A large variety of addressing mode typically from 5 to 20 different modes
3. Some instructions that perform specialized tasks and are used frequently
4. Variable length instruction format
5. Instructions that manipulate operands in memory.
6. Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions
7. Usually implemented as micro programmed control to tackle the variable length instructions.
8. CISC systems shorten execution time by reducing the number of instructions per program

FETCH-DECODE AND EXECUTE CYCLE

BASIC OPERATIONAL CONCEPTS
Connections between the processor and the main memory

In Addition to the ALU and CU, The processor contains a number of register used for several different purposes.
The PC (Program Counter) contains the memory address of the instruction to be executed. During execution, the contents of the PC are updated to point to the next instruction. Every time that an instruction is to be executed, the program counter releases its contents to the internal bus and sends it to the memory address register.
The MAR (Memory Address Register) holds the address of the location to or from which data are to be transferred. As can be seen from the figure above, the connection of the MAR to the main memory is one-way or unidirectional.
The MDR (Memory Data Register) contains the data to be written or read out of the addressed location.
During the fetch operation, the MDR contains the instruction to be executed or data needed during execution. In write operation, MDR the data to be written into the main memory.
The IR (Instruction Register) contains the instruction that is being executed. Before the IR executes the instruction it needs to be decoded first. As soon as the content of the MDR is transferred to the IR, the decoding process commences. After decoding, execution of the instruction will take place.
Operating Steps
1. PC is set to point to the first instruction of the program (the operating system loads the memory address of the first instruction).
2. The contents of the PC are transferred to the MAR (which is automatically transmitted to the MM) and a Read signal is sent to the MM (Main Memory).
3. The addressed word is read out of MM and loaded into the MDR.
4. The contents of MDR are transferred to the IR. The instruction is ready to be decoded and executed.
5. During execution, the contents of the PC are incremented or updated to point to the next instruction.
Example
Enumerate the different steps needed to execute the machine instruction
ADD LOCA, R0
Assume that the instruction itself is stored in the main memory at location INSTR, and that this address is initially in register PC. The first two steps might be expressed as:
1. Transfer the contents of register PC to register MAR.
2. Issue a READ command to the main memory, and then wait until it has transferred the requested word into register MDR.
CPU Instruction Execution Steps
Instruction execution in a CPU can now be summarized by the following steps:
1. Fetching the instruction from the memory into the instruction register.
2. Incrementing the PC to point to the next instruction to be executed.
3. Determining the type of instruction fetched (instruction decoding).
4. Determining the location of data in the memory. If the instruction uses data.
5. Fetching the required data into internal CPU registers.
6. Executing the instruction.
7. Storing the results in the designated locations.
8. Return to Step 1.
This is commonly referred to as the fetch-decode-execute cycle.